1. Field of the Invention
The present invention relates to a terminal layer setting method for a semiconductor circuit having a plurality of circuit layers, storage media storing a terminal layer setting program, storage media storing a circuit terminal extension processing program and a terminal extending component used for setting of the terminal layer.
2. Description of the Related Art
In recent years, with a quantum leap increase in the number of cells (e.g., logic gate, inverter and NAND) or macros (e.g., SRAM) which are equipped onto a board, separate layers for wiring between these cells and macros have evolved to a plurality of layers, parallel with, and independent of, the board itself.
With regard to a semiconductor circuit having such a plurality of layers, the problem is which of the plurality of layers to go through when connecting a cell or macro with the cell or macro for the respective mating connections as noted in a patent document 1 below for instance.
[Patent document 1] Japanese patent laid-open application publication No. 4-251964, “Automatic Layout Method”
In setting up a wiring layer (i.e., terminal layer) at an extending destination of a wiring terminal for a cell or macro, however, the extending destination has conventionally been set up on the lower layers close to the board in many cases, prioritizing a versatility of the cell or macro. Such practices have created a lot of circuit wiring, also in lower circuit layers, that is, in a local layer with a large resistance, and using of a lot of Vias (also called “contact hole”), and thus caused delayed circuit operation.
As shown by FIG. 1, as a delay time increases a slew rate of wave form increases, that is, the wave form becoming smoothly shouldered. And the delay time increases in proportion with the wiring capacitance of the circuit (i.e., cell or macro) or the resistance of wiring between the aforementioned circuit and that of the connecting destination, which is well known. In other words, as a wave travels through a circuit with a large wiring capacity or resistance, the wave loses its form rapidly as shown by FIG. 1.